1. Field of the Invention
The present invention relates to a technique for communicating information by means of synchronized transmit and receive devices.
2. Description of the Prior Art
Various types of integrated circuits require timing information to enable them to transmit and receive digital information at the proper time. For example, an audio CODEC (COder DECoder) used in telephone systems converts an analog signal from a microphone in a telephone set to a digital signal for transmission over a network, and conversely converts a digital signal from the network to an analog signal that drives an earphone or speaker in the telephone set. Video CODECs that perform comparable functions for video interface devices and digital video networks are also coming into use, along with various types of shared audio-video devices and networks. In most cases, the networks provide synchronous communications to and from the CODECs, so that a defined relationship in time exists between the transmitted digital signals from the devices on the network, and similarly for the received digital signals. Furthermore, a defined time relationship usually exists between the digital signals transmitted from, and received by, a given CODEC. However, it is also usually necessary to be able to change the desired time relationships, as when adding new terminal equipment to the network, or even from one telephone call to the next, as for providing network switching of the calls or for optimum utilization of the time slots available for transmission.
A typical multi-CODEC system is illustrated in FIG. 1. The CODECs 101, 102, 103 and 104 transmit digital signals over a common output line 105, and receive digital signals over a common input line 106. Each CODEC is assigned a time slot for transmission, and a time slot for reception, over the common lines. The transmit frame synchronization pulses, designated FST, provide the CODECs with timing information for transmitting their digitized information. For example, when synchronization pulse FST is received by a given CODEC, that CODEC then sends out a word of digitized information (not shown) to the line 105. In the case of a typical audio CODEC, this is often an 8-bit word, representing 2.sup.13 signal levels (i.e., 13 bits) that are compressed into the 8 bits. Similarly, when a receive frame synchronization pulse FSR is received by a CODEC, that CODEC is activated to accept a word of digitized information from the line 106. In this manner, each CODEC is instructed what portion (i.e., time slot) of a given frame of data to utilize for transmission and reception. The transmit signal TX on output line 105, and the input signal RX on line 106, may be communicated over separate conductors to the network if desired. Alternatively, they may be combined on a single bidirectional conductor, in which case both transmit frames and receive frames are communicated over the same conductor.
In a typical system, a total of 32 (or alternatively 64) time slots are available in a given "frame" of data, as illustrated in FIG. 2. A typical telephone channel is sampled at a rate of 8 kHz, thereby providing a new sample word every 125 microseconds. Therefore, the frame is 125 microseconds in duration. As indicated above, a receive synchronization pulse (FSR) is used to determine which of the 32 receive time slots in a receive frame provides dam to a given CODEC. Similarly, a transmit synchronization pulse (FST) is used to determine which of the 32 transmit time slots in a transmit frame is used for transmitting data from a given CODEC. For example, considering that the synchronization pulses are shown as they travel toward the CODEC (i.e., right to left) in FIG. 1, it can be seen that synchronization pulses FST.sub.0 and FSR.sub.0 cause CODEC 101 to first transmit a word of information, and thereafter receive a word of information. This is due to the delay .increment.T between FST0 and FSR.sub.0. This is also the case for CODEC 102, except that its synchronization pulses (FST.sub.1, FSR.sub.1) occur earlier in time than those for CODEC 101. On the other hand, CODEC 103 is instructed to transmit a word by synchronization pulse FST2, and to receive a word by synchronization pulse FSR.sub.2, at a later time than CODEC 101. The CODEC 104 is instructed to transmit and receive by synchronization pulses FST.sub.3 and FSR.sub.3 still later in time.
Various time relationships between the transmit and receive synchronization pulses are possible. Since the group of four CODECs shown in FIG. 1 communicate over a common transmit conductor (105) and receive conductor (106), the time delay .increment.T is typically the same for each CODEC. However, the time delay .increment.T may differ from one system design to the next. In fact, .increment.T may differ from one group of CODECs to another, even on the same system, depending on which "backplane" they communicate with. Furthermore, it is not in general necessary for the transmit synchronization pulses (FST) to arrive before the receive synchronization pulses (FSR); rather, the reverse could be the case, depending on system design. In fact, the synchronization pulses could arrive simultaneously in some designs (e.g., .increment.T=0), so that the CODECs simultaneously transmitted and received digital signals over the lines 105, 106. Therefore, it is desirable for the CODECs to be able to work with a wide range of .increment.T values.
Providing the synchronization pulses to the CODECs is usually accomplished through dedicated terminals on the integrated circuit containing the CODEC. That is, a first terminal is dedicated to the receive synchronization pulse (FSR), whereas a second terminal is dedicated to the transmit synchronization pulse (FST). However, a trend in integrated circuit design is to include more functionality on a given integrated circuit chip. Therefore, multiple CODECs may be included on a single chip in some cases. This may lead to a problem in packaging the chip, since additional package terminals are required. It is therefore desirable to be able to supply the synchronization pulses to the various CODECs on the chip using a minimum number of terminals. In one design, registers are included on the chip that are loaded with the transmit and receive timing information. These registers may be loaded through a single package terminal. However, the size of the integrated circuit undesirably increases to accommodate the registers. Furthermore, the use of registers may limit flexibility of use in many cases, since appropriate circuitry must be provided for interfacing the registers to a control circuit, such as a microprocessor for example.